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PADAUK FPPA core devices (16 bit)

These devices feature a 16-bit wide code memory. Byte order is little endian. The instruction set is called SYM_83A or SYM_83B2 in Padauk include files. The SDCC backend will be called pdk16.

16-bit FPPA instruction set
Hex	1 5	1 4	1 3	1 2	1 1	1 0	9	8	7	6	5	4	3	2	1	0	Mnemonic	ZF ?	CF ?	AC ?	OV ?	Description

0x0000	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	NOP					No operation

	0	0	0	0	0	0	0	0	0	0	0	1	opcode				Miscellaneous instructions
0x0010	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	ADDC A	ZF	CF	AC	OV	A ← A + CF
0x0011	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	1	SUBC A	ZF	CF	AC	OV	A ← A - CF
0x0012	0	0	0	0	0	0	0	0	0	0	0	1	0	0	1	0	IZSN A	ZF	CF	AC	OV	Increment A and skip next instruction if A is zero
0x0013	0	0	0	0	0	0	0	0	0	0	0	1	0	0	1	1	DZSN A	ZF	CF	AC	OV	Decrement A and skip next instruction if A is zero
0x0014	0	0	0	0	0	0	0	0	0	0	0	1	0	1	0	0	?
0x0015	0	0	0	0	0	0	0	0	0	0	0	1	0	1	0	1	?
0x0016	0	0	0	0	0	0	0	0	0	0	0	1	0	1	1	0	?
0x0017	0	0	0	0	0	0	0	0	0	0	0	1	0	1	1	1	PCADD A					Add A to PC
0x0018	0	0	0	0	0	0	0	0	0	0	0	1	1	0	0	0	NOT A	ZF				A ← ~A
0x0019	0	0	0	0	0	0	0	0	0	0	0	1	1	0	0	1	NEG A	ZF				A ← NEG(A)
0x001A	0	0	0	0	0	0	0	0	0	0	0	1	1	0	1	0	SR A		CF			A ← A >> 1
0x001B	0	0	0	0	0	0	0	0	0	0	0	1	1	0	1	1	SL A		CF			A ← A << 1
0x001C	0	0	0	0	0	0	0	0	0	0	0	1	1	1	0	0	SRC A		CF			A ← CF:A >> 1
0x001D	0	0	0	0	0	0	0	0	0	0	0	1	1	1	0	1	SLC A		CF			A ← A:CF << 1
0x001E	0	0	0	0	0	0	0	0	0	0	0	1	1	1	1	0	SWAP A					Swap the high nibble and low nibble of A
0x001F	0	0	0	0	0	0	0	0	0	0	0	1	1	1	1	1	DELAY A					Delay A+1 cycles, at end A ← 0

	0	0	0	0	0	0	0	0	0	0	1	1	opcode				Miscellaneous instructions
0x0030	0	0	0	0	0	0	0	0	0	0	1	1	0	0	0	0	WDRESET					Reset Watchdog timer
0x0031	0	0	0	0	0	0	0	0	0	0	1	1	0	0	0	1	?
0x0032	0	0	0	0	0	0	0	0	0	0	1	1	0	0	1	0	PUSHAF					Push A and flags to stack: [SP] ← A, [SP + 1] ← F, SP ← SP + 2
0x0033	0	0	0	0	0	0	0	0	0	0	1	1	0	0	1	1	POPAF	ZF	CF	AC	OV	Pop A and flags from stack: SP ← SP + 2, F ← [SP + 1], [SP] ← A
0x0034	0	0	0	0	0	0	0	0	0	0	1	1	0	1	0	0	?
0x0035	0	0	0	0	0	0	0	0	0	0	1	1	0	1	0	1	RESET					Reset the whole chip
0x0036	0	0	0	0	0	0	0	0	0	0	1	1	0	1	1	0	STOPSYS					System halt (OSC disabled)
0x0037	0	0	0	0	0	0	0	0	0	0	1	1	0	1	1	1	STOPEXE					CPU halt (OSC active to output clock, SYSCLK disabled to save power)
0x0038	0	0	0	0	0	0	0	0	0	0	1	1	1	0	0	0	ENGINT					Global interrupt enbale
0x0039	0	0	0	0	0	0	0	0	0	0	1	1	1	0	0	1	DISGINT					Global interrupt disable
0x003A	0	0	0	0	0	0	0	0	0	0	1	1	1	0	1	0	RET					Return from subroutine
0x003B	0	0	0	0	0	0	0	0	0	0	1	1	1	0	1	1	RETI					Return from interrupt
0x003C	0	0	0	0	0	0	0	0	0	0	1	1	1	1	0	0	MUL					Multiply (if available)
0x003D	0	0	0	0	0	0	0	0	0	0	1	1	1	1	0	1	?
0x003E	0	0	0	0	0	0	0	0	0	0	1	1	1	1	1	0	?
0x003F	0	0	0	0	0	0	0	0	0	0	1	1	1	1	1	1	?

	0	0	0	0	0	0	0	0	0	1							Miscellaneous instructions
0x004. 0x005.	0	0	0	0	0	0	0	0	0	1	0	k	k	k	k	k	PMODE k					Set PMODE k (if available)
0x0060	0	0	0	0	0	0	0	0	0	1	1	0	n	n	n	n	POPWPC n					Pop word PC(core n) from stack (if available)
0x0070	0	0	0	0	0	0	0	0	0	1	1	1	n	n	n	n	PUSHWPC n					Push word PC(core n) to stack (if available)

	0	0	0	0	0	0	0	0	c		6-bit IO addr						Operations with A and IO
0x008. ... 0x00B.	0	0	0	0	0	0	0	0	1	0	IO						MOV IO, A					IO ← A
0x00C. ... 0x00F.	0	0	0	0	0	0	0	0	1	1	IO						MOV A, IO	ZF				A ← IO

	0	0	0	0	opcode			9-bit MEM addr									16 bit memory operations
0x02.. 0x03..	0	0	0	0	0	0	1	M								0	STT16 M					Timer16 ← M (last bit of M set to 0, M must be word aligned)
0x02.. 0x03..	0	0	0	0	0	0	1	M								1	LDT16 M					M ← Timer16 (last bit of M set to 1, M must be word aligned)
0x04.. 0x05..	0	0	0	0	0	1	0	M								0	POPW M					Pop word from stack to memory M (last bit of M set to 0, M must be word aligned) (if available)
0x05.. 0x05..	0	0	0	0	0	1	0	M								1	PUSHW M					Push word from memory M to stack (last bit of M set to 1, M must be word aligned) (if available)
0x06.. 0x07..	0	0	0	0	0	1	1	M								0	IGOTO M					TODO (last bit of M set to 0, M must be word aligned) (if available)
0x06.. 0x07..	0	0	0	0	0	1	1	M								1	ICALL M					TODO (last bit of M set to 1, M must be word aligned) (if available)
0x08.. 0x09..	0	0	0	0	1	0	0	M								0	IDXM M, A					[M] ← A (last bit of M set to 0, M must be word aligned), 2 cycles
0x08.. 0x09..	0	0	0	0	1	0	0	M								1	IDXM A, M					A ← [M] (last bit of M set to 1, M must be word aligned), 2 cycles
0x0A.. 0x0B..	0	0	0	0	1	0	1	M								0	LDTABL M					A ← LowByte@CodeMem(M) (last bit of M set to 0, M must be word aligned), 2 cycles
0x0A.. 0x0B..	0	0	0	0	1	0	1	M								1	LDTABH M					A ← HighByte@CodeMem(M) (last bit of M set to 1, M must be word aligned), 2 cycles

	0	0	0	0	1	1	1	c	8-bit immediate								Operations with 8-bit literal
0x0E..	0	0	0	0	1	1	1	0	k								DELAY k					Delay k+1 cycles, at end A ← 0
0x0F..	0	0	0	0	1	1	1	1	k								RET k					A ← k and return from subroutine

	0	0	0	1	0	0	0	0	0	c	6-bit IO addr						Operations with A and IO
0x1000 ... 0x103F	0	0	0	1	0	0	0	0	0	0	IO						XOR IO, A					IO ← IO ^ A
0x1040 ... 0x107F	0	0	0	1	0	0	0	0	0	1	IO						XOR A, IO	ZF				A ← A ^ IO

	0	0	0	1	0	1	c	9-bit MEM addr									Operations with A and memory
0x14.. 0x15..	0	0	0	1	0	1	0	M									CNEQSN M, A	ZF	CF	AC	OV	Skip next instruction if M is not equal to A (flags changed according to (M-A))
0x16.. 0x17..	0	0	0	1	0	1	1	M									CNEQSN A, M	ZF	CF	AC	OV	Skip next instruction if M is not equal to A (flags changed according to (A-M))

	0	0	0	1	1	opcode			8-bit immediate								Operations with A and 8-bit literal
0x18..	0	0	0	1	1	0	0	0	k								ADD A, k	ZF	CF	AC	OV	A ← A + k
0x19..	0	0	0	1	1	0	0	1	k								SUB A, k	ZF	CF	AC	OV	A ← A - k
0x1A..	0	0	0	1	1	0	1	0	k								CEQSN A, k	ZF	CF	AC	OV	Skip next instruction if A equals k
0x1B..	0	0	0	1	1	0	1	1	k								CNEQSN A, k	ZF	CF	AC	OV	Skip next instruction if A not equals k
0x1C..	0	0	0	1	1	1	0	0	k								AND A, k	ZF				A ← A & k
0x1D..	0	0	0	1	1	1	0	1	k								OR A, k	ZF				A ← A \| k
0x1E..	0	0	0	1	1	1	1	0	k								XOR A, k	ZF				A ← A ^ k
0x1F..	0	0	0	1	1	1	1	1	k								MOV A, k					A ← k

	0	0	1	0	c			bit pos			6-bit IO addr						Bit operations with IO
0x20.. 0x21..	0	0	1	0	0	0	0	n			IO						T0SN IO.n					Test bit n of IO and skip next instruction if clear
0x22.. 0x23..	0	0	1	0	0	0	1	n			IO						T1SN IO.n					Test bit n of IO and skip next instruction if set
0x24.. 0x25..	0	0	1	0	0	1	0	n			IO						SET0 IO.n					Clear bit n of IO
0x26.. 0x27..	0	0	1	0	0	1	1	n			IO						SET1 IO.n					Set bit n of IO
0x28.. 0x29..	0	0	1	0	1	0	0	n			IO						TOG IO.n					Toggle bit n of IO
0x2A.. 0x2B..	0	0	1	0	1	0	1	n			IO						WAIT0 IO.n					Stop execution until bit n of IO is low
0x2C.. 0x2D..	0	0	1	0	1	1	0	n			IO						WAIT1 IO.n					Stop execution until bit n of IO is high
0x2E.. 0x2F..	0	0	1	0	1	1	1	n			IO						SWAPC IO.n		CF			Swap bit IO.n with CF is high

	0	0	opcode					9-bit MEM addr									Operations with A and memory
0x30.. 0x31..	0	0	1	1	0	0	0	M									NMOV A, M	ZF				A ← NEG(M)
0x32.. 0x33..	0	0	1	1	0	0	1	M									NMOV M, A					M ← NEG(A)
0x34.. 0x35..	0	0	1	1	0	1	0	M									NADD A, M	ZF	CF	AC	OV	A ← M + NEG(A)
0x36.. 0x37..	0	0	1	1	0	1	1	M									NADD M, A	ZF	CF	AC	OV	M ← NEG(M) + A
0x38.. 0x39..	0	0	1	1	1	0	0	M									CEQSN A, M	ZF	CF	AC	OV	Skip next instruction if M is equal to A (flags changed according to (A-M))
0x3A.. 0x3B..	0	0	1	1	1	0	1	M									CEQSN M, A	ZF	CF	AC	OV	Skip next instruction if A is equal to M (flags changed according to (M-A))
0x3C.. 0x3D..	0	0	1	1	1	1	0	M									COMP A, M	ZF	CF	AC	OV	Compare A with M (flags changed according to (A-M))
0x3E.. 0x3F..	0	0	1	1	1	1	1	M									COMP M, A	ZF	CF	AC	OV	Compare M with A (flags changed according to (M-A))
0x40.. 0x41..	0	0	1	0	0	0	0	M									ADD M, A	ZF	CF	AC	OV	M ← M + A
0x42.. 0x43..	0	0	1	0	0	0	1	M									ADD A, M	ZF	CF	AC	OV	A ← A + M
0x44.. 0x45..	0	0	1	0	0	1	0	M									SUB M, A	ZF	CF	AC	OV	M ← M - A
0x46.. 0x47..	0	0	1	0	0	1	1	M									SUB A, M	ZF	CF	AC	OV	A ← A - M
0x48.. 0x49..	0	0	1	0	1	0	0	M									ADDC M, A	ZF	CF	AC	OV	M ← M + A + CF
0x4A.. 0x4B..	0	0	1	0	1	0	1	M									ADDC A, M	ZF	CF	AC	OV	A ← A + M + CF
0x4C.. 0x4D..	0	0	1	0	1	1	0	M									SUBC M, A	ZF	CF	AC	OV	M ← M - A - CF
0x4E.. 0x4F..	0	0	1	0	1	1	1	M									SUBC A, M	ZF	CF	AC	OV	A ← A - M - CF
0x50.. 0x51..	0	0	1	1	0	0	0	M									AND M, A	ZF				M ← M & A
0x52.. 0x53..	0	0	1	1	0	0	1	M									AND A, M	ZF				A ← A & M
0x54.. 0x55..	0	0	1	1	0	1	0	M									OR M, A	ZF				M ← M \| A
0x56.. 0x57..	0	0	1	1	0	1	1	M									OR A, M	ZF				A ← A \| M
0x58.. 0x59..	0	0	1	1	1	0	0	M									XOR M, A	ZF				M ← M ^ A
0x5A.. 0x5B..	0	0	1	1	1	0	1	M									XOR A, M	ZF				A ← A ^ M
0x5C.. 0x5D..	0	0	1	1	1	1	0	M									MOV M, A					M ← A
0x5E.. 0x5F..	0	0	1	1	1	1	1	M									MOV A, M	ZF				A ← M

	0	1	1	opcode				9-bit MEM addr									Operations with memory
0x60.. 0x61..	0	1	1	0	0	0	0	M									ADDC M	ZF	CF	AC	OV	M ← M + CF
0x62.. 0x63..	0	1	1	0	0	0	1	M									SUBC M	ZF	CF	AC	OV	M ← M - CF
0x64.. 0x65..	0	1	1	0	0	1	0	M									IZSN M	ZF	CF	AC	OV	M ← M + 1 , skip next instruction if M is 0
0x66.. 0x67..	0	1	1	0	0	1	1	M									DZSN M	ZF	CF	AC	OV	M ← M - 1 , skip next instruction if M is 0
0x68.. 0x69..	0	1	1	0	1	0	0	M									INC M	ZF	CF	AC	OV	M ← M + 1
0x6A.. 0x6B..	0	1	1	0	1	0	1	M									DEC M	ZF	CF	AC	OV	M ← M - 1
0x6C.. 0x6D..	0	1	1	0	1	1	0	M									CLEAR M					M ← 0
0x6E.. 0x6F..	0	1	1	0	1	1	1	M									XCH M					Exchange A with M
0x70.. 0x71..	0	1	1	1	0	0	0	M									NOT M	ZF				M ← ~M
0x72.. 0x73..	0	1	1	1	0	0	1	M									NEG M	ZF				M ← NEG(M)
0x73.. 0x75..	0	1	1	1	0	1	0	M									SR M		CF			M ← M >> 1
0x76.. 0x77..	0	1	1	1	0	1	1	M									SL M		CF			M ← M << 1
0x78.. 0x79..	0	1	1	1	1	0	0	M									SRC M		CF			M ← CF:M >> 1
0x7A.. 0x7B..	0	1	1	1	1	0	1	M									SLC M		CF			M ← M:CF << 1
0x7C.. 0x7D..	0	1	1	1	1	1	0	M									SWAP M					Swap the high nibble and low nibble of M
0x7E.. 0x7F..	0	1	1	1	1	1	1	M									DELAY M					Delay M+1 cycles, at end A ← 0

	1	0	c		bit pos			9-bit MEM addr									Bit operations with memory
0x8...	1	0	0	0	n			M									T0SN M.n					Test bit n of memory M and skip next instruction if clear
0x9...	1	0	0	1	n			M									T1SN M.n					Test bit n of memory M and skip next instruction if set
0xA...	1	0	1	0	n			M									SET0 M.n					Clear bit n of memory M
0xB...	1	0	1	1	n			M									SET1 M.n					Set bit n of memory M

	1	1	c	k													Control transfers
0xC000 ... 0xDFFF	1	1	0	k													GOTO k					Jump to k (address in words, 2 cycles)
0xE000 ... 0xFFFF	1	1	1	k													CALL k					Call subroutine k (address in words, 2 cycles)

The icall and igoto instructions have been found in the datasheets of some older, no longer available devices, such as the PES331, only.

Instruction support by device
Device	#FPPA	ICALL	IGOTO	MUL	PMODE N	PUSHW pcN	PUSHW M	POPW M	POPW PCn
DF329	8	?	?	?	?	?	?	?	?
DF69	8	-	-	Y	Y	Y	Y	Y	Y
MCS11	8	-	-	Y	Y	Y	Y	Y	Y
MF520	8	?	?	?	?	?	?	?	?
MF610	8	?	?	?	?	?	?	?	?
MF616	8	?	?	?	?	?	?	?	?
PFC460	4	-	-	Y	Y	-	Y	Y	-
PFC886	8	-	-	-	Y	Y	Y	Y	Y
PFC887	8	?	?	?	?	?	?	?	?
PMC232	2	-	-	-	-	-	-	-	-
PMC234	2	-	-	-	-	-	-	-	-
PMC251	2	-	-	-	-	-	-	-	-
PMC271	2	-	-	-	-	-	-	-	-
PMC884	8	-	-	Y	Y	Y	Y	Y	Y
PMS232	2	-	-	-	-	-	-	-	-
PMS234	2	-	-	-	-	-	-	-	-
PMS271	2	-	-	-	-	-	-	-	-

While the PFC886 does not have the mul instruction, it does have hardware support for 8x16 and 16x16 multiplication and 16/16 division. The MF520 and MF616 are preprogrammed versions of the PFC886.