Free PDK | Free PDK is an effort to create an open source alternative to the proprietary Padauk µC programmer, as well as adding support to SDCC for Padauk µCs.

PADAUK FPPA core devices (13 bit)

These devices feature a 13-bit wide code memory. Byte order is little endian. The instruction set is called SYM_84B in Padauk include files. The SDCC backend is called pdk13.

13-bit FPPA instruction set
Hex	1 2	1 1	1 0	9	8	7	6	5	4	3	2	1	0	Mnemonic	ZF ?	CF ?	AC ?	OV ?	Description

0x0000	0	0	0	0	0	0	0	0	0	0	0	0	0	NOP					No operation
0x0006	0	0	0	0	0	0	0	0	0	0	1	1	0	LDSPTL					A ← LowByte@CodeMem(WORD[SP])
0x0007	0	0	0	0	0	0	0	0	0	0	1	1	1	LDSPTH					A ← HighByteB@Codemem(WORD[SP])

	0	0	0	0	0	0	0	opcode						Miscellaneous instructions
0x0010	0	0	0	0	0	0	0	0	1	0	0	0	0	ADDC A	ZF	CF	AC	OV	A ← A + CF
0x0011	0	0	0	0	0	0	0	0	1	0	0	0	1	SUBC A	ZF	CF	AC	OV	A ← A - CF
0x0012	0	0	0	0	0	0	0	0	1	0	0	1	0	IZSN A	ZF	CF	AC	OV	Increment A and skip next instruction if A is zero
0x0013	0	0	0	0	0	0	0	0	1	0	0	1	1	DZSN A	ZF	CF	AC	OV	Decrement A and skip next instruction if A is zero
0x0014	0	0	0	0	0	0	0	0	1	0	1	0	0	?
0x0015	0	0	0	0	0	0	0	0	1	0	1	0	1	?
0x0016	0	0	0	0	0	0	0	0	1	0	1	1	0	?
0x0017	0	0	0	0	0	0	0	0	1	0	1	1	1	PCADD A					Add A to PC
0x0018	0	0	0	0	0	0	0	0	1	1	0	0	0	NOT A	ZF				A ← ~A
0x0019	0	0	0	0	0	0	0	0	1	1	0	0	1	NEG A	ZF				A ← NEG(A)
0x001A	0	0	0	0	0	0	0	0	1	1	0	1	0	SR A		CF			A ← A >> 1
0x001B	0	0	0	0	0	0	0	0	1	1	0	1	1	SL A		CF			A ← A << 1
0x001C	0	0	0	0	0	0	0	0	1	1	1	0	0	SRC A		CF			A ← CF:A >> 1
0x001D	0	0	0	0	0	0	0	0	1	1	1	0	1	SLC A		CF			A ← A:CF << 1
0x001E	0	0	0	0	0	0	0	0	1	1	1	1	0	SWAP A					Swap the high nibble and low nibble of A
0x001F	0	0	0	0	0	0	0	0	1	1	1	1	1	?

0x0030	0	0	0	0	0	0	0	1	1	0	0	0	0	WDRESET					Reset Watchdog timer
0x0031	0	0	0	0	0	0	0	1	1	0	0	0	1	?
0x0032	0	0	0	0	0	0	0	1	1	0	0	1	0	PUSHAF					Push A and flags to stack: [SP] ← A, [SP + 1] ← F, SP ← SP + 2
0x0033	0	0	0	0	0	0	0	1	1	0	0	1	1	POPAF	ZF	CF	AC	OV	Pop A and flags from stack: SP ← SP + 2, F ← [SP + 1], [SP] ← A
0x0034	0	0	0	0	0	0	0	1	1	0	1	0	0	?
0x0035	0	0	0	0	0	0	0	1	1	0	1	0	1	RESET					Reset the whole chip
0x0036	0	0	0	0	0	0	0	1	1	0	1	1	0	STOPSYS					System halt (OSC disabled)
0x0037	0	0	0	0	0	0	0	1	1	0	1	1	1	STOPEXE					CPU halt (OSC active to output clock, SYSCLK disabled to save power)
0x0038	0	0	0	0	0	0	0	1	1	1	0	0	0	ENGINT					Global interrupt enbale
0x0039	0	0	0	0	0	0	0	1	1	1	0	0	1	DISGINT					Global interrupt disable
0x003A	0	0	0	0	0	0	0	1	1	1	0	1	0	RET					Return from subroutine
0x003B	0	0	0	0	0	0	0	1	1	1	0	1	1	RETI					Return from interrupt
0x003C	0	0	0	0	0	0	0	1	1	1	1	0	0	MUL					Multiply (if available)
0x003D	0	0	0	0	0	0	0	1	1	1	1	0	1	?
0x003E	0	0	0	0	0	0	0	1	1	1	1	1	0	?
0x003F	0	0	0	0	0	0	0	1	1	1	1	1	1	?

	0	0	0	0	0	c			5-bit IO addr					Operations with A and IO
0x006. 0x007.	0	0	0	0	0	0	1	1	IO					XOR IO, A					IO ← IO ^ A
0x008. 0x009.	0	0	0	0	0	1	0	0	IO					MOV IO, A					IO ← A
0x00A. 0x00B.	0	0	0	0	0	1	0	1	IO					MOV A, IO	ZF				A ← IO

	0	0	0	0	0	opcode			5-bit MEM addr					16 bit memory operations
0x00C. 0x00D.	0	0	0	0	0	1	1	0	M				0	STT16 M					Timer16 ← M (last bit of M set to 0, M must be word aligned)
0x00C. 0x00D.	0	0	0	0	0	1	1	0	M				1	LDT16 M					M ← Timer16 (last bit of M set to 1, M must be word aligned)
0x00E. 0x00F.	0	0	0	0	0	1	1	1	M				0	IDXM M, A					[M] ← A (last bit of M set to 0, M must be word aligned, 2 cycles)
0x00E. 0x00F.	0	0	0	0	0	1	1	1	M				1	IDXM A, M					A ← [M] (last bit of M set to 1, M must be word aligned, 2 cycles)

	0	0	0	0	1	8-bit immediate								Return with A
0x01..	0	0	0	0	1	k								RET k					A ← k and return from subroutine

	0	0	0	1	c	bit pos			c	4-bit MEM addr				Bit operations with memory
0x02..	0	0	0	1	0	n			0	M				T0SN M.n					Test bit n of memory M and skip next instruction if clear
0x02..	0	0	0	1	0	n			1	M				T1SN M.n					Test bit n of memory M and skip next instruction if set
0x03..	0	0	0	1	1	n			0	M				SET0 M.n					Clear bit n of memory M
0x03..	0	0	0	1	1	n			1	M				SET1 M.n					Set bit n of memory M

	0	0	1	opcode				6-bit MEM addr						Operations with A and memory
0x04..	0	0	1	0	0	0	0	M						ADD M, A	ZF	CF	AC	OV	M ← M + A
0x04..	0	0	1	0	0	0	1	M						SUB M, A	ZF	CF	AC	OV	M ← M - A
0x04..	0	0	1	0	0	1	0	M						ADDC M, A	ZF	CF	AC	OV	M ← M + A + CF
0x04..	0	0	1	0	0	1	1	M						SUBC M, A	ZF	CF	AC	OV	M ← M - A - CF
0x05..	0	0	1	0	1	0	0	M						AND M, A	ZF				M ← M & A
0x05..	0	0	1	0	1	0	1	M						OR M, A	ZF				M ← M \| A
0x05..	0	0	1	0	1	1	0	M						XOR M, A	ZF				M ← M ^ A
0x05..	0	0	1	0	1	1	1	M						MOV M, A					M ← A
0x06..	0	0	1	1	0	0	0	M						ADD A, M	ZF	CF	AC	OV	A ← A + M
0x06..	0	0	1	1	0	0	1	M						SUB A, M	ZF	CF	AC	OV	A ← A - M
0x06..	0	0	1	1	0	1	0	M						ADDC A, M	ZF	CF	AC	OV	A ← A + M + CF
0x06..	0	0	1	1	0	1	1	M						SUBC A, M	ZF	CF	AC	OV	A ← A - M - CF
0x07..	0	0	1	1	1	0	0	M						AND A, M	ZF				A ← A & M
0x07..	0	0	1	1	1	0	1	M						OR A, M	ZF				A ← A \| M
0x07..	0	0	1	1	1	1	0	M						XOR A, M	ZF				A ← A ^ M
0x07..	0	0	1	1	1	1	1	M						MOV A, M	ZF				A ← M

	0	1	0	opcode				6-bit MEM addr						Operations with memory
0x08..	0	1	0	0	0	0	0	M						ADDC M	ZF	CF	AC	OV	M ← M + CF
0x08..	0	1	0	0	0	0	1	M						SUBC M	ZF	CF	AC	OV	M ← M - CF
0x08..	0	1	0	0	0	1	0	M						IZSN M	ZF	CF	AC	OV	M ← M + 1 , skip next instruction if M is 0
0x08..	0	1	0	0	0	1	1	M						DZSN M	ZF	CF	AC	OV	M ← M - 1 , skip next instruction if M is 0
0x09..	0	1	0	0	1	0	0	M						INC M	ZF	CF	AC	OV	M ← M + 1
0x09..	0	1	0	0	1	0	1	M						DEC M	ZF	CF	AC	OV	M ← M - 1
0x09..	0	1	0	0	1	1	0	M						CLEAR M					M ← 0
0x09..	0	1	0	0	1	1	1	M						XCH M					Exchange A with M
0x0A..	0	1	0	1	0	0	0	M						NOT M	ZF				M ← ~M
0x0A..	0	1	0	1	0	0	1	M						NEG M	ZF				M ← NEG(M)
0x0A..	0	1	0	1	0	1	0	M						SR M		CF			M ← M >> 1
0x0A..	0	1	0	1	0	1	1	M						SL M		CF			M ← M << 1
0x0B..	0	1	0	1	1	0	0	M						SRC M		CF			M ← CF:M >> 1
0x0B..	0	1	0	1	1	0	1	M						SLC M		CF			M ← M:CF << 1
0x0B..	0	1	0	1	1	1	0	M						CEQSN A, M	ZF	CF	AC	OV	Skip next instruction if M is equal to A
0x0B..	0	1	0	1	1	1	1	M						?

	0	1	1	c		bit pos			5-bit IO addr					Bit operations with IO
0x0C..	0	1	1	0	0	n			IO					T0SN IO.n					Test bit n of IO and skip next instruction if clear
0x0D..	0	1	1	0	1	n			IO					T1SN IO.n					Test bit n of IO and skip next instruction if set
0x0E..	0	1	1	1	0	n			IO					SET0 IO.n					Clear bit n of IO
0x0F..	0	1	1	1	1	n			IO					SET1 IO.n					Set bit n of IO

	1	0	opcode			8-bit immediate								Operations with A and 8-bit literal
0x10..	1	0	0	0	0	k								ADD A, k	ZF	CF	AC	OV	A ← A + k
0x11..	1	0	0	0	1	k								SUB A, k	ZF	CF	AC	OV	A ← A - k
0x12..	1	0	0	1	0	k								CEQSN A, k	ZF	CF	AC	OV	Skip next instruction if A equals k
0x13..	1	0	0	1	1	k								?
0x14..	1	0	1	0	0	k								AND A, k	ZF				A ← A & k
0x15..	1	0	1	0	1	k								OR A, k	ZF				A ← A \| k
0x16..	1	0	1	1	0	k								XOR A, k	ZF				A ← A ^ k
0x17..	1	0	1	1	1	k								MOV A, k					A ← k

	1	1	c	k										Control transfers
0x1800 ... 0x1BFF	1	1	0	k										GOTO k					Jump to k (address in words, 2 cycles)
0x1C00 ... 0x1FFF	1	1	1	k										CALL k					Call subroutine k (address in words, 2 cycles)

There seem to be no optional instructions in this instruction set, there is no known implementation that supports MUL.

Instruction support by device
Device	#FPPA
PMC150	1
PMC153	1
PMC156	1
PMC166	1
PMS150	1
PMS150B	1
PMS150C	1
PMS150G	1
PMS153	1
PMS156	1
PMS15A	1
PMS15B	1